1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly relates to a level shift circuit functioning as an interface between circuits operating at different power source voltages.
2. Description of the Related Art
Conventionally, when connecting logic circuits having different power source voltages, it is necessary to shift the logic level of an output signal from one logic circuit to the level of the other logic circuit receiving the output signal.
A level shift circuit is a circuit used for such a purpose. Typical examples will be shown below.
FIG. 6 is a circuit diagram of an example of a level shift circuit of the related art.
In FIG. 6, the level shift circuit comprises an inverter I1 which operates by a power source voltage (3V) of a circuit of the input side and four transistors PT1, PT2, NT1, and NT2 which operate by a power source voltage (6V) of a circuit of the output side. The transistors PT1 and T2 are comprised of p-channel MOS (PMOS) transistors, and the transistors NT1 and NT2 are comprised of n-channel MOS (NMOS) transistors.
An input terminal TIN is connected to a gate of the transistor NT1 and the input of an inverter I1, while an output of the inverter I1 is connected to a gate of the transistor NT2. A source of the transistor NT1 is grounded, while the drain is connected to an output terminal TOUT, a drain of the transistor PT1, and a gate of the transistor PT2.
A source of the transistor NT2 is grounded, while the drain is connected to a drain of the transistor PT2 and a gate of the transistor PT1.
Note that, in this example, the logic level of the input signal SIN is 3V at a high (H) level and is 0V at a low level (0V), while the logic level of the output signal SOUT is 6V at a high (H) level and 0V at a low (L) level.
In such a configuration, when the logic level of the input signal SIN is H, the transistor NT1 turns on. Accordingly, the potential at the gate of the transistor NT2 falls, so the potential at the drain of the transistor PT2 rises.
At this time, because the potential at the gate falls, the transistor PT1 functions to lower the potential of the output terminal TOUT more reliably, while an L level signal is output at the output terminal TOUT.
Also, since the input potential of the inverter I1 is high, the output of the inverter I1 becomes 0V and the transistor NT2 is in an off-state.
Conversely, when the logic level of the input signal SIN becomes L, the transistor NT1 turns off and the inverter I1 inverts the level and makes the output potential 3V. As a result, the transistor NT2 turns on and lowers the potential at the gate of the transistor PT1. Due to this, the potential at the drain of the transistor PT1 rises and the H level signal SOUT is output at the output terminal TOUT.
At this time, since the potential at the gate rises, the transistor NT2 functions to lower the potential at the drain (potential at gate of transistor PT1) more reliably.
In this way, the level shift circuit converts the input signal SIN from the logic circuit of a power source voltage of 3V to the output signal SOUT having a high logic level of 6V.
FIG. 7 is a circuit diagram of another example of a level shift circuit of the related art.
The level shift circuit in FIG. 7 comprises an inverter I1 which operates by a power source voltage (3V) of the input side of the circuit and six transistors PT1, PT2, PT3, PT4, NT1, and NT2 which operates by a power source voltage (6V) of the output side of a circuit.
In the level shift circuit in FIG. 7, in addition to the configuration of the level shift circuit of FIG. 6, the transistor PT3 comprised by a PMOS transistor is connected in series between the source of the transistor PT1 and the supply line of the power source voltage of 6V, while the transistor PT4 comprised by a PMOS transistor is connected in series between the source of the transistor PT2 and the supply line of the power source voltage of 6V.
A gate of the transistor PT3 is connected to the input terminal TIN, while a gate of the transistor PT4 is connected to the output of the inverter I1.
In such a configuration, when the logic level of the input signal SIN is H, the potential at the gate of the transistor PT3 rises and the transistor NT1 turns on. Therefore, the potential at the gate of the transistor PT2 falls and the potential at the drain of the transistor PT2 (common connection point of transistor PT2 and transistor NT2) rises.
At this time, since the potential at the gate rises, the transistor PT1 functions to lower the potential of the output terminal TOUT more reliably, and an L level signal SOUT is output at the output terminal TOUT.
Also, since the input potential of the inverter I1 is high, the output of the inverter I1 becomes 0V, the transistor NT is in an off-state, and the transistor PT4 is in an on-state.
Conversely, when the logic level of the input signal SIN becomes L, the potential at the gate of the transistor PT3 falls, the transistor NT1 turns off, and the inverter I2 inverts the level to make the output potential 3V. As a result, the potential at the gate of the transistor PT4 rises and the transistor NT2 turns on, thus the potential at the gate of the transistor PT1 falls.
Due to this, the potential at the drain of the transistor PT1 rises, and an H level signal SOUT is output at the output terminal TOUT.
At this time, since the potential at the gate rises, the transistor PT2 functions to lower the potential at the gate of the transistor PT1 more reliably.
In the level shift circuit, not only the transistors NT1 and NT2 but also the transistors PT3 and PT4 are directly driven by the input signal SIN. Therefore, by adjusting the sizes of the transistors with respect to the operating voltages, it is possible to improve the delay of the input signal which arises at the time of converting a level by the level shift circuit.
As explained above, the level shift circuit is capable of converting the input signal SIN from the logic circuit with the power source of 3V to the output signal SOUT having the H logic level of 6V.
In the level shift circuit in FIG. 6, however, the only transistors directly driven by the input signal are the transistors NT1 and NT2, therefore the operation performance of the level shift circuit is low.
For this reason, at the time of converting the level of the input signal, a large delay arises in the converted signal, which has a detrimental effect on the output side circuit. Alternatively, in the case where the difference of the power source voltages is large between the power source circuits respectively having different power source, it becomes unoperatable.
Namely, the level shift circuit shown in FIG. 6 cannot be used for an interface between high speed logic circuits which operate at different power source voltages. Further, the operatable voltage range is narrow.
On the other hand, in the level shift circuit in FIG. 7, not only the transistors NT1 and NT2 but also the transistors PT3 and PT4 are directly driven by the input signal, therefore it is possible to reduce the delay of the input signal which arises when this level shift circuit converts a level by adjusting the sizes of these transistors with respect to the operating voltages.
Due to this, it is possible to use the level shift circuit for an interface between high speed logic circuits operating at different power source voltages. The range of operating voltage is wide as well.
However, there are disadvantages that the number of transistors is increased compared with the circuit shown in FIG. 6 and, moreover, the size of the device itself cannot be reduced due to the properties of the circuit.
For example, in a circuit such as a decoder which requires several level shift circuits in one circuit, the area occupied by the level shift circuits becomes very large.
Also, since this circuit is comprised of three series-connected transistors, the performance of the circuit declines along with the reduction of the operating voltage and the delay at the conversion of an input signal sometimes becomes further larger than that of the level shift circuit shown in FIG. 6 when operating at a low voltage.
Namely, since the level shift circuit shown in FIG. 7 is comprised of series-connected PMOS transistors, it is not suitable for operating at a low voltage and cannot be expected to operate at a high speed at a wide range of power source voltages.